1. Technical Field
The invention relates to the field of multiprocessor systems, and more specifically placing commands on an inter-chip processor bus.
2. Description of Related Art
The basic structure of a conventional symmetric multi-processor computer system 10 is shown in FIG. 1. Computer system 10 has one or more processing units arranged in one or more processor groups; in the depicted system, there are four processing units 12a, 12b, 12c and 12d in processor group 14. The processing units communicate with other components of system 10 via a system or interchip link bus 16. Interchip link bus 16 is connected to one or more service processors 18a, 18b, a system memory device 20, and various peripheral devices 22. A processor bridge 24 can optionally be used to interconnect additional processor groups. System 10 may also include firmware (not shown) which stores the system's basic input/output logic, and seeks out and loads an operating system from one of the peripherals whenever the computer system is first turned on (booted).
System memory device 20 (random access memory or RAM) stores program instructions and operand data used by the processing units, in a volatile (temporary) state. Peripherals 22 may be connected to interchip link bus 16 via, e.g., a peripheral component interconnect (PCI) local bus using a PCI host bridge. A PCI bridge provides a low latency path through which processing units 12a, 12b, 12c and 12d may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access RAM 20. Such PCI devices may include a network adapter, a small computer system interface (SCSI) adapter providing interconnection to a permanent storage device (i.e., a hard disk), and an expansion bus bridge such as an industry standard architecture (ISA) expansion bus for connection to input/output (I/O) devices including a keyboard, a graphics adapter connected to a display device, and a graphical pointing device (mouse) for use with the display device.
In a symmetric multi-processor (SMP) computer, all of the processing units 12a, 12b, 12c and 12d are generally identical, that is, they all use a common set or subset of instructions and protocols to operate, and generally have the same architecture. As shown with processing unit 12a, each processing unit may include one or more processor cores 26a, 26b which carry out program instructions in order to operate the computer. An exemplary processor core includes the PowerPC™ processor marketed by International Business Machines Corp. which comprises a single integrated circuit superscalar microprocessor having various execution units, registers, buffers, memories, and other functional units, which are all formed by integrated circuitry. The processor cores may operate according to reduced instruction set computing (RISC) techniques, and may employ both pipelining and out-of-order execution of instructions to further improve the performance of the superscalar architecture.
Each processor core 12a, 12b includes an on-board (L1) cache (actually, separate instruction cache and data caches) implemented using high speed memory devices. Caches are commonly used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from system memory 20. A processing unit can include another cache, such as a second level (L2) cache 28 which, along with a memory controller 30, supports both of the L1 caches that are respectively part of cores 26a and 26b. Additional cache levels may be provided, such as an L3 cache 32 which is accessible via interchip link bus 16. Each cache level, from highest (L1) to lowest (L3) can successively store more information, but at a longer access penalty. For example, the on-board L1 caches in the processor cores might have a storage capacity of 128 kilobytes of memory, L2 cache 28 might have a storage capacity of 512 kilobytes, and L3 cache 32 might have a storage capacity of 2 megabytes. To facilitate repair/replacement of defective processing unit components, each processing unit 12a, 12b, 12c, 12d may be constructed in the form of a replaceable circuit board, pluggable module, or similar field replaceable unit (FRU), which can be easily swapped installed in or swapped out of system 10 in a modular fashion. A command unit is a generic term that includes, among others, processor cores, and the service processors (which may also be called flexible service processor).
It is axiomatic that the more parts there are to a device, the more opportunities there are to break one or more parts. Consequently, complex systems of microprocessors have relied on more commands being transported that are concerned, instead of with customer data, with error detection, system maintenance, reliability, accessibility and serviceability. Often these commands need be dispatched rapidly, in order to limit the impact of an error to certain parts of the system, and to rapidly reform and remedy the situation.
In systems where multiple microprocessors depend on a common bus to transmit commands, there is a problem that the limited bandwidth of the bus permits only simplex communication from a processor to one or more recipient processors. In other words, each processor needed to contend with other processors to use the interchip link bus. Moreover, a prior art single processor, with multiple commands, would need to queue such commands for iterative dispatch along the interchip link bus. It has become increasingly necessary to issue pervasive commands on the mainline or functional busses, rather than any the alternative slower specialized busses.
As the number of system-wide multi-chip pervasive functions grow, the ability to prioritize the additional interchip communication is important to handle such that the limited availability of the bus is maximized. Engineers now add a new function and require more inter-chip communication to accomplish it. The outcome is that chip I/O is increased, thus adding to chip size, complexity and as well as cost.